The present invention relates to a semiconductor device including a capacitor that has a capacitive insulating film formed out of a ferroelectric film, and also relates to a method for fabricating the device.
In recent years, performance of consumer electronic units is being more and more enhanced, because microcomputers, for example, are now able to operate at much higher speeds with much lower power consumed. To cope with the performance enhancement, semiconductor elements in a semiconductor device have been miniaturized rapidly. Thus, unwanted radiation, i.e., electromagnetic noise generated from the electronic units, is a serious problem.
To reduce the unwanted radiation, a technique of building a capacitor with large capacitance, in which a ferroelectric film with a high dielectric constant is used as a capacitive insulating film, in a semiconductor integrated circuit device, for example, is attracting much attention.
Also, the number of dynamic RAMs (DRAMs) integrated on a chip goes on increasing. In response, a technique of using high-dielectric-constant materials instead of silicon oxides or silicon nitrides, which have been used widely, is now researched broadly.
Further, a ferroelectric film exhibiting spontaneous polarization has also been researched and developed vigorously to implement a nonvolatile RAM that can operate with a lower voltage applied and that can also perform high-speed write and read operations.
The most important problem to be solved in implementing a semiconductor device with a capacitor including a ferroelectric capacitive insulating film is increasing the number of DRAMs integrated on a chip without degrading the characteristic of the capacitor.
In particular, to use noble metals (e.g., Pt, Ir and the like) as electrode materials for a ferroelectric capacitor is a brand-new technique developed over the past few years. Therefore, there are still many problems left to successfully apply this technique to semiconductor device processing for a capacitor including a ferroelectric capacitive insulating film. For example, adhesiveness of the electrode materials like Pt and Ir to an insulating film such as a silicon dioxide or silicon nitride film is not satisfactory. Therefore, the insulating film might peel off if annealing is performed at a high temperature. Also, depending on the type of the undercoat film, the insulating film might peel off right after the insulating film has been deposited. In view of these problems, a contact layer is needed between the Pt or Ir upper electrode and the insulating film of silicon dioxide or nitride. In the prior art, a titanium film, which has often been used in semiconductor device processing, is used as a contact layer.
Hereinafter, a known semiconductor device and a method for fabricating the device will be described with reference to the accompanying drawings.
FIG. 5 illustrates a cross-sectional structure of the principal portion of a known semiconductor device. As shown in FIG. 5, a lower electrode 11, a capacitive insulating film 12, an upper electrode 13 and a contact layer 14 are formed in this order on the semiconductor substrate 10. Each of the lower and upper electrodes 11 and 13 is made of a Pt film, the capacitive insulating film 12 is formed out of a ferroelectric film, and the contact layer 14 is made of a Ti film. And an insulating film 15 made of silicon dioxide or silicon nitride, for example, is deposited over the lower and upper electrodes 11 and 13, capacitive insulating film 12 and contact layer 14.
The lower electrode 11 is connected to a first metal interconnect 17A, which is formed on a part of the insulating film 15 and filled in a first contact hole 16A. And the upper electrode 13 is connected to a second metal interconnect 17B, which is formed on another part of the insulting film 15 and filled in a second contact hole 16B. Each of the first and second metal interconnects 17A and 17B is made up of a lower titanium nitride film and an upper aluminum film. Also, a passivation film 18 of silicon nitride is deposited over all the members described above.
Hereinafter, a method for fabricating the known semiconductor device will be described with reference to FIGS. 6A through 6F.
First, as shown in FIG. 6A, first Pt film 11A, ferroelectric film 12A, second Pt film 13A and Ti film 14A are deposited in this order over a semiconductor substrate 10. Then, the Ti and second Pt films 14A and 13A are patterned to form a contact layer 14 out of the Ti film 14A and an upper electrode 13 out of the second Pt film 13A, respectively, as shown in FIG. 6B.
Next, the ferroelectric and first Pt films 12A and 11A are patterned, thereby forming a capacitive insulating film 12 out of the ferroelectric film 12A and a lower electrode 11 out of the first Pt film 11A, respectively, as shown in FIG. 6C.
Subsequently, as shown in FIG. 6D, an opening 12a is formed in a region of the capacitive insulating film 12 in which a first contact hole 16A will be defined. Then, an insulating film 15 is deposited over the entire surface of the semiconductor substrate 10. Next, the first and second contact holes 16A and 16B are opened through the insulating film 15 to partially expose the lower and upper electrodes 11 and 13, respectively.
The next step is depositing a multilayer structure consisting of a lower titanium nitride film and an upper aluminum film over the insulating film 15 in such a manner that the first and second contact holes 16A and 16B are filled in by the multilayer structure. Then, the multilayer structure is patterned to form the first metal interconnect 17A connected to the lower electrode 11 and the second metal interconnect 17B connected to the upper electrode 13, respectively, as shown in FIG. 6E.
Next, a passivation film 18 of silicon nitride is deposited over the entire surface of the semiconductor substrate 10. In this manner, the known semiconductor device as shown in FIG. 6F is obtained. Although not shown in the drawings, after making openings in the passivation film 18, electrode pads connected to the first and second metal interconnects 17A and 17B are formed. As a result, a series of process steps of fabricating the known semiconductor device is completed.
After the contact layer 14, upper electrode 13, capacitive insulating film 12 and lower electrode 11 are formed by patterning, annealing is usually performed to repair the damage caused by the patterning of the capacitive insulating film 12.
However, as a result of the annealing, Ti atoms that make up the contact layer 14 might diffuse through column-like crystals of Pt in the upper electrode 13 to reach the ferroelectric capacitive insulating film 12. In that case, the polarization properties of the ferroelectric capacitive insulating film 12 might degrade and electrical characteristic of the capacitor including the capacitive insulating film 12 might deteriorate.
In addition, as a result of the annealing, the contact layer 14 will expand, while the upper electrode 13 will shrink. Therefore, a void might be formed in the upper electrode 13 because stress is applied to the upper electrode 13.